[1] The highest-performance Crusoe chip, the TM5400, is 73 mm² in area. It contains a 128KB level one (L1) cache and a 256KB level two (L2) cache, on-chip LongRun power control, an integrated peripheral-component-interface bus and double- and standard-data-rate dynamic RAM controllers.

The chips were fabricated by IBM Corp. at its foundry in Burlington, Vt. They feature five levels of copper interconnect and a minimum feature size of 0.18 µm.

(ILLUSTRATIONS: TRANSMETA CORP.)

IEEE Spectrum May 2000 Volume 37 Number 5